Uses JTAG, for testing and in-system programming (ISP) printed circuit boards and systems.

Silicon debug, JTAG, boundary scan, IEEE 1149.1, scan-based electronic design verification, and test solutions from Intellitech Corporation.

EDA start up offering a physical design solution claiming guaranteed accurate prediction and delivery of the best possible timing results, without iterations.

CAD EDA PCB Software

Visual Micro Lab is a new design tool for the ST6 micro. It allows you to build applications without the need of an emulator.

Avertec is a new company specialising in the commercialisation of innovative VLSI verification tools developed in University research laboratories. Its main areas of expertise are in hierarchical timing analysis and the automatic abstraction of behavioural model from circuit netlists.